ASEArch - Algorithms and Software for Emerging Architectures

Xeon Phi

The Xeon Phi is the product name for Intel's first generation MIC (Many Integrated Core) architecture, the Knights Corner.

Knights Corner MIC supports the new IMCI (Intel Many Core Instruction set) with 512 bit wide registers, has 61 cores (60 for compute, 1 for OS) and 4 in-order HW threads per core, with separate register files (32 512bit ZMM registers per HW thread). 32KB of L1 data cache is shared between threads of a core and 30MB of L2 cache is shared among the 60 cores. The L2 cache is a distributed 60 x 512KB coherent cache with a wide ring bus topology. Programming tools and languages include OpenMP, OpenCL, Cilk/CilkPlus, Intel's Fortran/C/C++ compiler and math and MPI librares. Learn more...


 Knights Corner